Well known current steering digital-to-analog converters (DACs) utilize a plurality of current cells for providing a set of well defined currents (i.e. bit currents) controlled by a digital input code, and a plurality of current switches for selectively switching individual ones of the bit currents generated by the current cells through an output resistor such that the weighted sum of currents passing through the output resistor results in an analogue output voltage proportional to the number of current switches which are enabled (i.e. the number of logic high bits of the digital input code).
MOS-based self-calibrated current cells have been in use in current-steering digital-to-analog converters to copy a reference current to several current cells. This basic technique is attractive because of its simplicity, but suffers from several limitations. These limitations include errors due to charge injection and clock feed-through from the digital switches incorporated in the current cells, leakage current from the switches, finite output resistance due to channel length modulation in the output transistors, etc. Some prior art current cells utilize a cascode device to increase the output resistance of the cell and to reduce the coupling of output back to the storage node of the output transistor. However, it has been found that this approach reduces the available voltage swing for the output transistor.
According to one aspect of the present invention, a CMOS-based current cell is provided having higher output resistance than prior art MOS-based current cells, as well as smaller minimum voltage and improved accuracy.
According to one alternative embodiment of the invention, the self-calibrated current cell is implemented using BiCMOS circuitry.
As discussed above, the constant current generated by respective current cells in a current-steering DAC are selectively switched through the output resistor via respective current switches. Prior art bipolar current switches are known to suffer from error in the output current due to the finite current gain of the bipolar switch transistors. As a result, the output current of these prior art current switches differs from the actual bit current generated by its associated current cell by an amount equal to the base current of the bipolar switching transistor. One prior art approach to minimizing this error is to use a Darlington-connected pair of bipolar transistors. However, this approach tends to significantly degrade the switching speed of the circuit.
On the other hand, MOS-based current switches are known to have the advantage of avoiding non-linearity due to base-current mismatches in prior art bipolar transistor switches. However, the MOS devices have a substantially lower transconductance than the bipolar devices for the same current and area, which means it takes a larger voltage swing at the input to switch the current. Since the bit line which carries the input digital code can be loaded with large parasitic capacitance, the overall switching speed of such prior art MOS-based current switches can be significantly degraded.
Therefore, according to another aspect of the present invention, a BiCMOS current switch is provided having no base current error, and which achieves approximately twice the switching speed when compared to prior art MOS current switches.